Hello this will be an experts questions:) You should be familiar with the following topics • Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL) • Serial-ATA Gen1, Gen2 and Gen3, especially Out-of-Band (OOB) communication Question: How should a GTXE2 be configured for Serial-ATA? OOB signaling is not working neither RX_ElectricalIdle nor ComInit. Introduction: I implemented a SATA controller for my final bachelor project, which supports multiple vendor/device platforms (Xilinx Virtex-5, Altera Stratix II, Altera Stratix IV). Boris Fx Continuum Complete Serial.

'The Serial ATA Host Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices.

'Features The Nuvation Serial ATA Host Controller includes the following features: Compliant to the Serial ATA AHCI 1.0 specification, with 32 command slots per port. In order to store massive image data in real-time system, a high performance Serial Advanced Technology Attachment[1] (SATA) controller is proposed in this paper. Serial ATA (SATA) and Serial Attached SCSI (SAS) are data storage protocol standards that have the primary function of transferring data.

Now it's time to port this controller to the next device family: Xilinx 7-Series devices, by name a Kintex-7 on a KC705 board. The SATA controller has a additional abstraction layer in the physical layer, which is based on SAPIS and PIPE 3.0.

So to port the SATA controller to a new device family, I have only to write a new transceiver wrapper for a GTXE2 MGT. As of Xilinx's CoreGenerator doesn't support the SATA protocols in the CoreGen wizard, I started a transceiver project from scratch and applied all necessary settings as far as they are asked by the wizard. Adobe Photoshop Cs6 Ita Cracker. After that I copied the GTXE2_COMMON instantiation into my wrapper module, ordered the generics and ports into a meaning full schema. As a third step I connected all unconnected ports (the wizards doesn't assign all values!!) to their default values (the default from UG476 or zero if not defined). In step 4 I checked all generics and ports again against the UG476 if they are compatible to the SATA settings. After that I connected my wrapper ports to the MGT and inserted cross-clock modules if necessary. As of the KC705 board has no 150 MHz reference clock, I program the Si570 to supply this clock as 'ProgUser_Clock' after each board 'bootup'.